WCET of Cortex‑M7 loops with cache and branch prediction
Summary The core objective is to perform Worst-Case Execution Time (WCET) estimation for a bare-metal loop running on an ARM Cortex-M7 microcontroller. Despite the absence of interrupts and multitasking, the presence of a non-deterministic hardware pipeline—specifically the Instruction Cache (I-Cache) and the Dynamic Branch Predictor—makes traditional cycle-counting inaccurate. The challenge lies in the fact that … Read more