Spinlock vs Condvar: Why the Fast Path Can Hurt Scaling
Summary During the development of a high-throughput circuit simulator, a performance regression occurred when transitioning from a condition variable (condvar) signaling mechanism to a lock-free spinlock architecture. While the initial implementation was bottlenecked by OS scheduler overhead (200 kHz), the lock-free approach collapsed performance by orders of magnitude when scaling to multiple cores, despite showing … Read more